Integrated tensile strained silicon nfet and compressive strained silicon-germanium pfet implemented in finfet technology

ABSTRACT

A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.14/705,291 filed May 6, 2015, the disclosure of which is herebyincorporated by reference.

TECHNICAL FIELD

The present invention relates to integrated circuits and, in particular,to a field effect transistor (FET) device fabricated using a fin ofsemiconductor material wherein NFET devices utilize tensile strainedsilicon fin material and PFET devices utilize compressive strainedsilicon-germanium fin material.

BACKGROUND

It is recognized by those skilled in the art that tensile strainedsilicon (Si) material provides for increased electron mobility andimproved performance with respect to n-channel metal oxide semiconductor(MOS) field effect transistor (FET) devices. However, many integratedcircuit designs require the use of p-channel MOSFET devices as well.Circuits of this type are commonly referred to as complementary metaloxide semiconductor (CMOS) circuits. Unfortunately, tensile strainedsilicon material is detrimental to the operation of p-channel MOSFETdevices which instead prefer compressive strained silicon-germanium(SiGe) material to boost hole mobility and improve performance. Theintegration of tensile strained silicon material and compressivestrained silicon-germanium material on a common substrate in support ofthe fabrication of CMOS circuits has proven to be a challenge.

The prior art teaches the formation of integrated circuits which utilizeFinFET type field effect transistors. The FinFET transistor comprises achannel region which is oriented to conduct an electrical currentparallel to the surface of the substrate. The channel region is providedin an elongated section of semiconductor material referred to as a“fin.” The source and drain regions of the transistor are formed in theelongated section on either side of the channel region. A gate is placedto straddle over and on both opposed sides of the elongated section atthe location of the channel region to provide control over theconductive state of the transistor. This FinFET design is well suitedfor manufacturing a multi-channel transistor in which multiple elongatedsections are formed in parallel to define neighboring channel regionswhich are separated from each other by an intermediate gate portion ofthe transistor gate spanning with a perpendicular orientation over themultiple elongated sections.

It is preferred for the fabrication of CMOS circuits with FinFET devicesfor the elongated section of semiconductor material (i.e., the fin) ofthe n-channel MOSFET devices to be made of tensile strained siliconmaterial and for the elongated section of semiconductor material (i.e.,the fin) of the p-channel MOSFET devices to be made of compressivestrained silicon-germanium (SiGe) material. It has proven difficult,however, to obtain relaxation of the tensile strained silicon materialon a substrate in order to support the formation of compressive strainedsilicon-germanium material. In other words, provision of both tensilestrained silicon material and compressive strained silicon-germaniummaterial on a substrate for supporting fins of CMOS circuits ischallenging.

A need accordingly exists in the art for a method of manufacture whichcan integrate both tensile strained silicon material and compressivestrained silicon-germanium material for the formation of CMOS FinFETdevices.

SUMMARY

In an embodiment, tensile strained silicon semiconductor fins areprovided in a first area of the substrate for use in producing finFETtransistors of a first conductivity type, while compressive strainedsilicon-germanium semiconductor fins are provided in a second area ofthe substrate for use in producing finFET transistors of a secondconductivity type.

In an embodiment, an integrated circuit comprises: a substrate includinga first area and a second area; a plurality of tensile strained siliconsemiconductor fins in the first area of the substrate; a plurality ofcompressive strained silicon-germanium semiconductor fins in the secondarea of the substrate; a first metal gate extending over the pluralityof tensile strained silicon semiconductor fins in the first area; and asecond metal gate extending over the plurality of compressive strainedsilicon-germanium semiconductor fins in the second area; wherein saidplurality of compressive strained silicon-germanium semiconductor finscomprise tensile strained silicon semiconductor material that has beenrelaxed and into which germanium has been driven.

In an embodiment, an integrated circuit comprises: a substrate includinga first area and a second area; a first plurality of semiconductor finsin the first area of the substrate; a second plurality of semiconductorfins in the second area of the substrate; wherein the first and secondpluralities of semiconductor fins are formed from a layer of siliconsemiconductor material that is tensile strained and patterned to definethe first and second pluralities of semiconductor fins; and wherein thesilicon semiconductor material of the second plurality of semiconductorfins has relaxed tensile strain in comparison to the siliconsemiconductor material of the first plurality of semiconductor fins andfurther includes germanium which is not present in the first pluralityof semiconductor fins; a first metal gate extending over the firstplurality of semiconductor fins in the first area; and a second metalgate extending over the second plurality of semiconductor fins in thesecond area.

In an embodiment, an integrated circuit comprises: a substrate includinga first area and a second area; a plurality of tensile strained siliconsemiconductor fins in the first area of the substrate; a plurality ofcompressive strained silicon-germanium semiconductor fins in the secondarea of the substrate; a first metal gate extending over the pluralityof tensile strained silicon semiconductor fins in the first area; and asecond metal gate extending over the plurality of compressive strainedsilicon-germanium semiconductor fins in the second area.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the embodiments, reference will now bemade by way of example only to the accompanying figures in which:

FIGS. 1-21B illustrate process steps in the formation of CMOS FinFETdevices.

DETAILED DESCRIPTION OF THE DRAWINGS

Reference is now made to FIGS. 1-21B which illustrate the process stepsin the formation of CMOS FinFET devices. It will be understood that thedrawings do not necessarily show features drawn to scale.

FIG. 1 shows a silicon on insulator (SOI) semiconductor substrate 10comprising a semiconductor substrate 12, an insulating layer 14 and atensile strained silicon semiconductor layer 16 in a stack of a wafer.Such a substrate is commonly referred to in the art by the acronym sSOIwherein the lower case “s” refers to the term “strained.” The tensilestrained silicon semiconductor layer 16 may be doped in accordance withthe application, or alternatively may be un-doped in which case the sSOIsubstrate 10 is of the “fully-depleted” type. The tensile strainedsemiconductor layer 16 may, for example, have a thickness of 30-50 nm.The insulating layer 14 is commonly referred to in the art as a buriedoxide (BOX) layer. The substrate 10 includes an area 18 which isreserved for the formation of first polarity (for example, n-channel)devices (NFET) and an area 20 which is reserved for the formation ofsecond, opposite, polarity (for example, p-channel) devices (PFET).

A hard mask 30 comprising a layer of silicon nitride (SiN) 34 is thendeposited on the semiconductor layer 16. The silicon nitride layer 34may, for example, be deposited using a chemical vapor deposition (CVD)process with a thickness of, for example, approximately 20 nm. Theresult is shown in FIG. 2.

A lithographic process as known in the art is then used to define aplurality of fins 50 from the tensile strained silicon semiconductorlayer 16. The hard mask 30 is patterned to leave mask material 36 at thedesired locations of the fins 50. An etching operation, such as ananisotropic dry etch, is then performed through the mask to openapertures 52 in the layer 16 on each side of each fin 50. In a preferredembodiment with the sSOI substrate, for example, the etch defining thefins 50 extends to a depth which reaches the insulating layer 14. Eachfin 50 is accordingly comprised of a tensile strained siliconsemiconductor fin region 16′ and the mask material 36. The fins 50 mayhave a width of 6-12 nm and a pitch of 25-30 nm (with a spacing betweenadjacent fins of 17-22 nm). The result of the etching process for finformation is shown in FIG. 3.

A conformal deposit of a layer 60 of silicon oxide (SiO₂) is then madeusing an atomic layer deposition technique. The layer 60 may have athickness of approximately 3 nm. See, FIG. 4. A directional etch, suchas a reactive ion etch (RIE), is then performed to define an oxidesidewall spacer 62 on each side of each fin 50. The result is shown inFIG. 5.

A conformal deposit of a layer 70 of silicon nitride (SiN) is then madeusing an atomic layer deposition technique. The layer 70 may have athickness of approximately 3 nm. See, FIG. 6. A directional etch, suchas a reactive ion etch (ME), is then performed to define a nitridesidewall spacer 72 on each side of each fin 50. The result is shown inFIG. 7.

A conformal deposit of a layer 80 of silicon oxide (SiO₂) is then madeusing an atomic layer deposition technique. The layer 80 may have athickness of approximately 10 nm. See, FIG. 8. Following the deposit oflayer 80, the wafer is subjected to an anneal (for example, at atemperature of 1050° C. for 30 seconds) in order to effectuate adensification of the deposited oxide sidewall spacers 62 and nitridesidewall spacers 72. Densification in this case advantageously hardensthe silicon oxide material so to make that material more difficult toremove or recess using conventional etch processes such as HF, COR orhot phosphoric acid.

The area 18 reserved for the formation of n-channel devices (NFET) isthen blocked off with a lithographic masking process and the area 20reserved for the formation of p-channel devices (PFET) is opened(reference 82). This opening of the area 20 includes the removal of thelayer 80 and the nitride sidewall spacers 72. Any resist present fromthe lithographic process to block off area 18 is then removed. Theresult is shown in FIG. 9.

It will be noted that an optional conformal deposit of a layer ofsilicon oxide (SiO₂) can be made at least with respect to the openedarea 20 so as to cover and protect the mask material 36 for each fin 50.This layer is not explicitly shown in FIG. 9.

Next, a deposition of tensile strained silicon nitride (SiN) is made tofill the area 20. The deposit of silicon nitride material, as known inthe art, can be tuned to provide either tensile or compressive stress byproperly selecting the deposition parameters (temperature, pressure,etc.). A chemical-mechanical polishing (CMP) operation is then performedto planarize the tensile strained silicon nitride deposit at the top ofthe layer 80 of silicon oxide present in the area 18. The result is atensile strained silicon nitride block 90 covering the fins 50 in thearea 20 as shown in FIG. 10. For example, the tensile strain may rangefrom 500 MPa to 1.5 GPa.

The layer 80 of silicon oxide in the area 18 is then removed using aBHF/HF etch. The result is shown in FIG. 11. It will be noted that as aresult of the removal of layer 80 in the area 18, the tensile strainedsilicon nitride block 90 is fully cut-off from contact with the fins 50in area 18 (i.e., the block 90 is not directly contacting the fins 50 orthe sidewall spacers on the fins 50 in the area 18).

The substrate wafer is then subjected to a high temperature anneal (forexample, at a temperature of 1200° C. for 2 minutes) so as to relax thestrain in the area 20. This relaxation occurs due to the appliedtemperature and the close proximity of the tensile strained siliconnitride block 90 to the fins 50 in area 20 (i.e., the separation betweenmaterials is only by the thinned thickness of the sidewall spacers 62).As a result, the tensile strained silicon semiconductor fin region 16′of each fin 50 in area 20 is converted to a relaxed siliconsemiconductor fin region 116. Depending on initial strain, the region16′ may have a strain of 1-1.5 GPa, while the region 116 afterrelaxation may have a strain of about 100 MPa. The result is shown inFIG. 12. It will be noted that the tensile strained siliconsemiconductor fin region 16′ of each fin 50 in area 18 is not relaxed(or to the extent relaxation occurs, such relaxation is minimal (forexample, it will retain greater than 80% of its original strain) becausethere is no direct contact of the tensile strained silicon nitride block90 to the fins 50 in area 18.

Next, a deposition of silicon oxide (SiO₂) is made to fill the area 18.This deposition is made using a flowable oxide process. Achemical-mechanical polishing (CMP) operation is then performed toplanarize the silicon oxide deposit at the top of the tensile strainedsilicon nitride block 90 present in the area 20. The result is a siliconoxide block 92 covering the fins 50 in the area 18 as shown in FIG. 13.

The tensile strained silicon nitride block 90 is then removed fromcovering the fins 50 in area 20. This removal is accomplished, forexample, using a hot phosphorus etch that is selective to silicon oxide.An HF or COR etch process is then performed to remove silicon oxide.This process will remove all of the sidewall spacers 62 and maskmaterial 36 from the fins 50 in area 20, thus leaving the relaxedsilicon semiconductor fin regions 116, as well as remove all, orsubstantially all, of the silicon oxide block 92 covering the fins 50 inthe area 18. The result is shown in FIG. 14. It will be noted, however,that the mask material 36, sidewall spacers 72 and sidewall spacers 62covering the fins 50 in the area 18 remain in place to protect the fins50 in area 18 during the next processing operations performed on thefins 50 in area 20.

Two options are provided at this point with respect to the provision ofsilicon-germanium material in the region 20. In a first option, anepitaxial growth process is performed to grow an epitaxialsilicon-germanium region 120 on the relaxed silicon semiconductor finregions 116 as shown in FIG. 15A. In a second option, a non-selectiveepitaxy process is used to deposit an amorphous silicon-germanium layer122 to cover the relaxed silicon semiconductor fin regions 116 as shownin FIG. 15B. Although the amorphous layer 122 will also cover the fins50 in the area 18, it will be noted that the mask material 36, sidewallspacers 72 and sidewall spacers 62 remain in place to cover the fins 50.A condensation process is then performed to drive germanium from theregion 120 or layer 122 into the relaxed silicon semiconductor finregions 116 and produce compressively strained silicon germanium finregions 216. The condensation may, for example, comprise an oxidationprocess using a 900° C. oxidation followed by a 1000° C. N₂ anneal. Thesilicon oxide and/or germanium oxide produced from the condensationprocess are then removed. The result is shown in FIG. 16.

Using a sequence of hot phosphoric acid, hydrofluoric acid and hotphosphoric acid washes, the mask material 36, sidewall spacers 72 andsidewall spacers 62 for the fins 50 in the area 18 are removed. Theresult is shown in FIG. 17 with the area 18 including tensile strainedsilicon semiconductor fin regions 16′ and the area 20 includingcompressive strained silicon germanium fin regions 216. It will be notedthat if a concern exists with respect to consumption of the silicongermanium material of the compressive strained silicon germanium finregions 216 during the sequence of hot phosphoric acid, hydrofluoricacid and hot phosphoric acid washes, the compressive strained silicongermanium fin regions 216 may first be protected by a thin layer ofsilicon oxide (approximately 5 nm), with the silicon oxide layerlithographically processed and removed from area 18. The hot phosphoricacid wash is then used to remove the silicon nitride mask and spacer.The hydrofluoric acid wash is then used to remove silicon dioxide spacerand protection layer.

A sacrificial polysilicon material 240 is deposited using a conventionalchemical vapor deposition (CVD) process to cover the tensile strainedsilicon semiconductor fin regions 16′ and the compressive strainedsilicon germanium fin regions 216. The polysilicon material 240 may, inan alternative implementation, instead comprise amorphous silicon. Aconformal oxide (not explicitly shown) may be formed on the exposedsurfaces of the fin regions 16′ and 216 prior to deposition of thepolysilicon material 240. As understood by those skilled in the art, thepolysilicon material (with the oxide) is associated with the formationof structures commonly referred to as “dummy gate” structures. Thepolysilicon material of the dummy gate structures will be subsequentlyremoved later in the fabrication process and replaced with a metal gatestack defining the actual operating gate electrode for the transistordevices (this process referred to in the art as a “replacement metalgate (RMG)” process). Thus, there is no need to dope the polysiliconmaterial 240. The deposit of the polysilicon material 240 will have aheight in excess of the height of the fin regions 16′ and 216 so thatthe fins will be completely covered. The material 240 may have athickness, for example, of 60-100 nm. The top surface of the polysiliconmaterial 240 deposit is planarized using conventionalchemical-mechanical polishing (CMP) techniques to provide a planar topsurface.

A hard mask layer 242 with a thickness of 20-40 nm is deposited on theplanar top surface of the polysilicon material 240 using a chemicalvapor deposition (CVD) process. The layer 242 is lithographicallypatterned in a manner well known to those skilled in the art to leavemask material 244 at desired locations for the dummy gate structures. Areactive ion etch (ME) is then performed to open apertures 246 in thepolysilicon material on either side of the dummy gate 248. The structureof the dummy gate 248 may be considered to straddle over each of the finregions 16′ and 216, or over a plurality of adjacent fin regions, at achannel region (see, FIG. 18A).

A silicon nitride material is then conformally deposited, for example,using an atomic layer deposition (ALD) technique as known in the art,and subsequently etched preferentially on the horizontal surfaces toleave sidewall spacers 250 on the side walls of the polysilicon dummygates 248 (see, FIGS. 18B and 18C).

The dummy gate structure accordingly comprises a patterned polysilicon(or amorphous silicon) dummy gate 248, an overlying silicon nitride cap(formed by the mask material 244) and sidewall spacers 250. Although notspecifically shown in FIGS. 18B and 18C, dummy gate structures may alsobe formed at the ends of each of the fin regions 16′ and 216 inaccordance with the known technique of gate tuck-under.

Using an epitaxial process tool and starting from the exposed surfacesof the fin regions 16′ and 216, an epitaxial growth 270 of asilicon-based semiconductor material is made. The epitaxial growth 270extends above the top surface of the fins to regions adjacent thesidewall spacers 250 on either side of the dummy gate structures. Thesilicon-based epitaxial growth 270 may be in situ doped as needed for agiven application. As a result of the epitaxial growth 270, raisedsource and drain regions 272 and 274, respectively, are formed on eitherside of the dummy gate structures. The result is shown in FIGS. 19A-19B.The epitaxial growth 70 may comprise, for example: silicon orsilicon-carbide doped with phosphorous or arsenic to a dopingconcentration of 1×10²⁰ to 5×10²⁰ at/cm³ for the fin regions 16′ in theNFET area 18. The epitaxial growth 70 may comprise, for example:silicon-germanium doped with boron to a doping concentration of 1×10²⁰to 5×10²⁰ at/cm³ for the fin regions 216 in the PFET area 20.Appropriate lithographic masking processes as known in the art are usedto separately open the areas 18 and 20 to accommodate selectiveepitaxial growth in each region.

Reference is now made to FIGS. 20A-20B. A silicon dioxide material 280is deposited to cover the substrate. The material 280 may be furtherprocessed using conventional chemical-mechanical polishing (CMP)techniques to provide a planar top surface that stops at the top of eachdummy gate structure.

Using a selective removal process (such as an ammonium hydroxide etch),the dummy gates 248 are removed. The removed dummy gates 248 are thenreplaced with a metal gate structure 290. In an example, the metal gatestructure may comprise a high-K dielectric liner (forming the gatedielectric for the transistor) deposited using an atomic layerdeposition (ALD) process with a thickness of 1-2 nm, a work functionmetal deposited using a chemical vapor deposition process and a contactmetal fill deposited using a chemical vapor deposition process. Aninsulating cap 292 covers the metal gate structure 290. The result isshown in FIGS. 21A-21B.

Further processing well known to those skilled in the art is thenperformed to produce the metal contacts to the gate (metal gatestructure 290), source region 272 and drain region 274. For example,additional silicon dioxide material may be deposited to complete theformation of a pre-metallization dielectric (PMD) level for theintegrated circuit. This material may be further processed usingconventional chemical-mechanical polishing (CMP) techniques to provide aplanar top surface. A hard mask layer, for example an organicplanarization layer (OPL), is then deposited on the planar top surfaceof the PMD layer using a coating process. The OPL is thenlithographically patterned in a manner well known to those skilled inthe art to form openings at desired locations for making electricalcontact to the gate, source region and drain region. A reactive ion etch(ME) is then performed to open and extend apertures completely throughthe pre-metallization dielectric (PMD) to expose a top surface of thegate metal and the epitaxial growth of the source and drain regions. TheOPL is then removed. The apertures are then filled with metalmaterial(s) to define a contact made to each of the gate, source regionand drain region of the transistor. As necessary, a conventionalchemical-mechanical polishing (CMP) technique may be used to removeexcess metal so as to provide a planar top surface. The metal materialsdefining the contacts may, for example, comprise tungsten depositedusing a chemical vapor deposition process. The fabrication process iscompatible with the formation of a silicide at the bottom of the sourceand drain contacts. The techniques for salicidation are well known tothose skilled in the art. The silicide may, for example, comprise atypical nickel platinum silicide or alternatively a silicide arisingfrom the use of a titanium nitride liner for the contact.

At this point, front end of line (FEOL) fabrication of the integratedcircuit is complete. Further back end of line (BEOL) processing tofabricate metallizations and interconnects may then be performed as wellknown to those skilled in the art.

The foregoing description has provided by way of exemplary andnon-limiting examples a full and informative description of theexemplary embodiment of this invention. However, various modificationsand adaptations may become apparent to those skilled in the relevantarts in view of the foregoing description, when read in conjunction withthe accompanying drawings and the appended claims. However, all such andsimilar modifications of the teachings of this invention will still fallwithin the scope of this invention as defined in the appended claims.

What is claimed is:
 1. An integrated circuit, comprising: a substrateincluding a first area and a second area; a plurality of tensilestrained silicon semiconductor fins in the first area of the substrate;a plurality of compressive strained silicon-germanium semiconductor finsin the second area of the substrate, wherein said plurality ofcompressive strained silicon-germanium semiconductor fins comprisetensile strained silicon semiconductor material modified to relaxtensile strain and include germanium; a first metal gate extending overthe plurality of tensile strained silicon semiconductor fins in thefirst area; and a second metal gate extending over the plurality ofcompressive strained silicon-germanium semiconductor fins in the secondarea.
 2. The integrated circuit of claim 1, wherein the substrate is asilicon on insulator type substrate.
 3. The integrated circuit of claim1, wherein: the tensile strained silicon semiconductor fins and firstmetal gate form finFET transistors of a first conductivity type; and thecompressive strained silicon-germanium semiconductor fins and secondmetal gate form finFET transistors of a second conductivity type.
 4. Theintegrated circuit of claim 3, wherein the first conductivity type isn-type and the second conductivity type is p-type.
 5. An integratedcircuit, comprising: a substrate including a first area and a secondarea; a first plurality of semiconductor fins in the first area of thesubstrate; a second plurality of semiconductor fins in the second areaof the substrate; wherein the first and second pluralities ofsemiconductor fins are formed from a layer of silicon semiconductormaterial that is tensile strained and patterned to define the first andsecond pluralities of semiconductor fins; and wherein the siliconsemiconductor material of the second plurality of semiconductor fins hasrelaxed tensile strain in comparison to the silicon semiconductormaterial of the first plurality of semiconductor fins and furtherincludes germanium which is not present in the first plurality ofsemiconductor fins; a first metal gate extending over the firstplurality of semiconductor fins in the first area; and a second metalgate extending over the second plurality of semiconductor fins in thesecond area.
 6. The integrated circuit of claim 5, wherein the substrateis a silicon on insulator type substrate and the layer of siliconsemiconductor material is a top layer of said silicon on insulator typesubstrate.
 7. The integrated circuit of claim 5, wherein: the firstplurality of semiconductor fins and first metal gate form finFETtransistors of a first conductivity type; and the second plurality ofsemiconductor fins and second metal gate form finFET transistors of asecond conductivity type.
 8. The integrated circuit of claim 7, whereinthe first conductivity type is n-type and the second conductivity typeis p-type.
 9. An integrated circuit, comprising: a substrate including afirst area and a second area; a plurality of tensile strained siliconsemiconductor fins in the first area of the substrate; a plurality ofcompressive strained silicon-germanium semiconductor fins in the secondarea of the substrate; a first metal gate extending over the pluralityof tensile strained silicon semiconductor fins in the first area; and asecond metal gate extending over the plurality of compressive strainedsilicon-germanium semiconductor fins in the second area.
 10. Theintegrated circuit of claim 9, wherein the substrate is a silicon oninsulator type substrate.
 11. The integrated circuit of claim 9,wherein: the tensile strained silicon semiconductor fins and first metalgate form finFET transistors of a first conductivity type; and thecompressive strained silicon-germanium semiconductor fins and secondmetal gate form finFET transistors of a second conductivity type. 12.The integrated circuit of claim 11, wherein the first conductivity typeis n-type and the second conductivity type is p-type.